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Career History
Independant consultant, Dunedin, New Zealand. September 2006 - present
Providing independant consultancy services to the semiconductor industry.
Jennic Ltd., Sheffield, UK. SOC Engineer (March 2005 – July 2006)
* Project lead for development of pre-production test solution for complex radio device. Known issues with this device demand a re-spin for full production, however current device will be shipped in quantity for engineering samples and pre-production evaluation.
* Liaise with various external contract houses and partners to progress pre-production solution:
o Load board design and manufacture.
o Probe card design and manufacture.
o Full screening test program development with subsequent development of characterization suite.
* Design modifications for subsequent production device.
* Novel Design for Test development to enable full characterization of pre-production device.
* Familiarization with Agilent 93K Soc series ATE, including SmartTest program development.
Duolog Technologies Kft., Budapest, Hungary.
Design For test Team Lead (September 2004 – March 2005)
* Handled all day to day technical and man management aspects associated with a dedicated team of 4 DFT engineers.
* Provided all training requirements to enable individual team members to take ownership of specific project DFT tasks.
* Expanded role to take responsibility of additional design team members to allow the group to work in, synthesis, static timing, formal verification and layout.
* Managed client interface to ensure company status improvement and subsequent design service contracts.
* Provided ongoing communication to internal sales, marketing and engineering resource groups.
* Represented company at EuroDesign Conference 2004, and subsequently invited as technical panel member for EuroDesign Conference 2005.
Jennic Ltd., Sheffield, UK, SOC Engineer (Feb 2000 – September 2004)
* Technical Lead and Technical Project Manager for a complex radio device. Handled all aspects of the digital implementation and managed the interface from the mixed signal and radio groups into the SOC build flow.
* Responsible for implementation of a SPI4.2 to quad SPI3 bridge in 180nm. SPI4.2 PHY developed in standard cell technology, device complicated by non-standard I/O arrangements and requirements for flip-chip technology. Responsible for interface to the package substrate design teams – substrate design complexities magnified by need to have a single substrate design for future derivative developments.
* Presented company development for module based LogicBIST solution to ensure high quality components with minimal test overhead.
* Presented company development of an SOC level test mechanism to address the complexities of integrating multiple IP modules from various sources.
* Completed design and implementation of a microprocessor interface for an internal development (framer) for the telecommunications market.
* Instrumental in evaluation of industry tool offering to allow best in class point tool solution for the company SOC group.
Fujitsu Microelectronics Ltd., Manchester, UK. Design Engineer (March 1994 January 2000)
* Responsible for the successful implementation of over 25 ASIC developments in technologies ranging from 0.8micron to 0.25micron.
* Provided mentor role to junior engineers.
* Published company development associated with scan chain reordering. This methodology was adopted by Japan as a standard in-house flow for all ASIC developments.
* Instrumental in securing group work from Fujitsu Telecommunications group in Japan, based largely on layout expertise developed within the ASIC group in Manchester.
* Published company developments on integration of intellectual property.
* Provided regular tooling recommendations to development teams in Japan.
Nortel Networks, Monkstown, Northern Ireland.
Contract test technician (October 1993 – February 1994)
* Responsible for production line test of various boards associated with fibre-optic communication systems.
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